Deep Submicron Design Support Service

Deep sub micron design is full of pitfalls that can cause failure of your circuits: clock-skew and latency of interacting clocks, IR-drop on the power mesh, electro-migration problems, the growing importance of interconnect delays, crosstalk, on-chip variation, many metal interconnect layers...
IMEC's Design Support Service can help you achieve a first time right ASIC.

Features and Benefits

• Based on state-of-the art Synopsys Galaxy and Cadence Encounter platforms
  • Classical synthesis flow (diagram)
  • Semi-physical synthesis flow (diagram)
  • Full physical synthesis flow (diagram)
• Full design flow support
  • Analog design support
  • Specification to RTL code
  • RTL simulation, synthesis & verification
  • Design for test (DFT) and Automatic Test-Pattern Generation (ATPG)
  • Floorplanning & Virtual Prototyping
  • Hard IP block inclusion
  • Gated clock-tree synthesis
  • Routing
  • In-Place Optimization (IPO) and ECO iterations
  • Static Timing Analysis (STA) with or without on-chip variation (OCV)
  • Parasitic extraction
  • Sign-off timing checks
  • Tape-out checks: DRC, ERC, LVS...
  • Tape-out preparation
• Several entry points in the design flow
  • Specification
  • RTL (customer writes RTL code)
  • Netlist (customer performs RTL synthesis)
  • Placed netlist (customer performs physical synthesis)
  • GDSII (customer performs full or partial layout)
• The Design Support Service extends beyond the EUROPRACTICE technology and library offering. In the past foundries like Tower, Chartered, TSMC and ST have been targeted on top of the UMC and AMIS technologies offered by EUROPRACTICE. Apart from Virtual Silicon, libraries have been used from other library vendors like Artisan, Agere, ST...

Many circuits have been taped out, for 2 to 9 metal-layer processes, for in-house developed SoC's as well as for ASICS developed by third-party design houses, companies, research institutes and universities. Many of these systems held analog full-custom blocks, combined with other macro's (e.g. several kinds of RAM or ROM, PLL's, analog full-custom blocks …) and standard-cells. Circuit complexities of up to 71 million transistors were handled.