GaN-IC > Technologies
imec GaN-IC on SOI
GaN-ICs for the monolithic integration of power systems

 

Basic characteristics

Imec researchers have combined GaN-on-SOI technology with trench isolation for the monolithic integration of GaN-based devices. The aim has been to isolate the devices by trench etching through GaN and Si into the SiO2 buried layer, and as so enable the monolithic integration of GaN circuits, such as half-bridges.

In this technology, a GaN layer is epitaxially grown on a 200mm SOI wafer (Si(100)/SiO2/Si(111)) using metal-organic chemical vapor deposition (MOCVD). The stack consists of an AlN nucleation layer, an (Al)GaN buffer layer, a GaN channel layer, an AlGaN barrier layer and a Mg-doped p-GaN layer. Delicate strain engineering is performed to control the stress built up in the wafer during growth, resulting in a GaN-on-SOI wafer with controlled warpage and good mechanical strength.

Furthermore, e-mode p-GaN HEMTs can be processed and TiN/p-GaN stacks used for the gates.

 

Schematic cross section of e-mode p-GaN HEMTs
Figure 1: Schematic cross section of e-mode p-GaN HEMTs

 

Top view of a fabricated device
Figure 2. Top view of a fabricated device. A box-like isolation structure is created around each HEMT device.

 

Please refer to the following links for detailed information on the current state of this technology:

https://www.imec-int.com/en/imec-magazine/imec-magazine-june-2017/first-time-demonstration-of-fully-isolated-gan-power-devices-using-soi-technology

https://www.imec-int.com/en/articles/imec-world-first-to-develop-200v-and-650v-dispersion-free-normally-off-e-mode-power-devices-on-200mm-8-inch-si-wafers

 

Applications

GaN-IC designers target a wide range of applications in high power switching and power conversion.

 

MPW Runs

For information about participation in our MPW runs please refer to the related tabs.

 

Contacts

GaN-IC MPW Runs

Dedicated Prototype

Technical Questions

 

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