IP & Libraries > Standard cell libraries > faraday

Standard cell libraries -- Faraday

IMEC has signed an agreement with Faraday to distribute Faraday's UMC sponsored libraries (no GDS) under following conditions:

*Universities and research institutes can get access free of charge to Faraday libraries forUMC technologies for non-commercial design activities provided prototyping is done on MPW run. When tape-out is done on full mask set, tape-out fee applies as for companies

*Companies can get access to Faraday libraries for UMC technologies for commercial design activities provided a tape-out fee is paid to IMEC (when companies have a direct license from Faraday, this tape-out fee is waived)

 


ProcessIPIP NameDescription
L250 GIICore CellFS90A_C_GENERIC_CORECore cells
I/OFS90A_C_T33_GENERIC_IO FS90A_C_50VT_GENERIC_IO

True 2.5V I/O and 2.5V I/O with 3.3V tolerance (programmable)

True 3.3V I/O and 3.3V I/O with 5V tolerance (programmable)

1P SRAMFS90A_C_SUSynchronous, high speed single port RAM
1P RFFS90A_C_SYSynchronous, single port register file
2P RFFS90A_C_SZSynchronous, two port register file
VIA ROMFS90A_C_SPSynchronous, via1 programmable ROM
PLL IPPLL9019Phase locked loop




ProcessIPIP NameDescription
L180 GIICore CellFSA0A_C_GENERIC_CORECore cells
I/OFSA0A_C_T33_GENERIC_IO FSA0A_C_50VT_GENERIC_IOTrue 3.3V programmable I/O 3.3V programmable I/O with 5V tolerance
1P SRAMFSA0A_C_SUSynchronous, high speed single port RAM
Dual Port SRAMFSA0A_C_SJSynchronous, dual port RAM
1P RFFSA0A_C_SYSynchronous, single port register file
2P RFFSA0A_C_SZSynchronous, two port register file
VIA ROMFSA0A_C_SPSynchronous, via1 programmable ROM
PLL IPFXPLL031HA0A_BPGDPhase locked loop




ProcessIPIP NameDescription
L180 LLCore CellFSA0L_A_GENERIC_CORECore cells
I/OFSA0L_A_T33_GENERIC_IO FSA0L_A_50VT_GENERIC_IOTrue 3.3V programmable I/O 3.3V programmable I/O with 5V tolerance
1P SRAMFSA0L_A_SHSynchronous, high density single port RAM
Dual Port SRAMFSA0L_A_SJ (not available yet)Wait for UMC 8T bit cell to start design
1P RFFSA0L_A_SYSynchronous, single port register file
2P RFFSA0L_A_SZ (not available yet)Wait for UMC 8T bit cell to start design
VIA ROMFSA0L_A_SPSynchronous, via1 programmable ROM
PLL IPFXPLL010HA0L_APGDPhase locked loop










ProcessIPIP NameDescription
L130 HS/FSGCore CellFSC0H_D_GENERIC_CORECore cells
I/OFSC0H_D_T33_GENERIC_IO FSC0H_D_50VT_GENERIC_IOTrue 3.3V programmable I/O 3.3V programmable I/O with 5V tolerance
1P SRAMFSC0H_D_SHSynchronous, high density single port SRAM
Dual Port SRAMFSC0H_D_SJSynchronous, high density dual port SRAM
1P RFFSC0H_D_SYSynchronous, high speed single port register file
2P RFFSC0H_D_SZ Synchronous, two port register file
VIA ROMFSC0H_D_SPSynchronous, via1 programmable ROM
PLLFXPLL110HC0H_APGDPhase locked loop




ProcessIPIP NameDescription
L130 LL/FSGCore CellFSC0L_D_GENERIC_CORECore cells
I/OFSC0L_D_T33_GENERIC_IO FSC0L_D_50VT_GENERIC_IOTrue 3.3V programmable I/O 3.3V programmable I/O with 5V tolerance
1P SRAMFSC0L_D_SHSynchronous, low leakage single port SRAM
Dual Port SRAMFSC0L_D_SJSynchronous, low leakage dual port SRAM
1P RFFSC0L_D_SYSynchronous, low leakage single port register file
2P RFFSC0L_D_SZSynchronous, low leakage dual port register file
VIA ROMFSC0H_D_SPSynchronous, via1 programmable ROM
PLL IPFXPLL010HC0L_APGDPhase locked loop




ProcessIPIP NameDescription
L130E SP/FSGCore CellFSC0G_D_GENERIC_CORECore cells
I/OFSC0G_D_T33_GENERIC_IO FSC0G_D_50VT_GENERIC_IOTrue 3.3V programmable I/O 3.3V programmable I/O with 5V tolerance
1P SRAMFSC0G_D_SHSynchronous, standard performance single port SRAM
Dual Port SRAMFSC0G_D_SJSynchronous, standard performance dual port SRAM
1P RFFSC0G_D_SYSynchronous, standard performance single port register file
2P RFFSC0G_D_SZSynchronous, standard performance dual port register file
VIA ROMFSC0H_D_SPSynchronous, via1 programmable ROM
PLL IPFXPLL010HC0G_APGD (not available yet)Phase locked loop




ProcessIPIP NameDescription
L130E Fusion1P SRAMFSC0U_D_SHSynchronous, fusion single port SRAM
Dual Port SRAMFSC0U_D_SJSynchronous, fusion dual port SRAM
1P RFFSC0U_D_SYSynchronous, fusion single port register file
2P RFFSC0U_D_SZ Synchronous, fusion dual port register file
VIA ROMFSC0H_D_SPSynchronous, via1 programmable ROM
PLL IPFXPLL010HC0U_APGDPhase locked loop








ProcessIPIP NameDescription
L90 SP Low-K (RVT)Core CellFSD0A_B_GENERIC_CORECore cells
I/O (2.5V)FOD0A_B25_T25_GENERIC_IOTrue 2.5V programmable I/O
I/O (3.3V)FOD0A_B33_T33_GENERIC_IOTrue 3.3V programmable I/O
2.5V OD 3.3V I/O CellFOD0A_B25_T33_GENERIC_IO2.5V programmable I/O with 3.3V tolerance
1P SRAMFSD0A_B_SHSynchronous, single port SRAM
Dual Port SRAMFSD0A_B_SJSynchronous, dual port RAM
1P RFFSD0A_B_SYSynchronous, single port register file
2P RFFSD0A_B_SZSynchronous, dual port register file
VIA ROMFSD0A_B_SPSynchronous, via1 programmable ROM
PLL IPFXPLL110HD0APhase locked loop




ProcessIPIP NameDescription
L90 LL Low-K (RVT)Core CellFSD0K_A_GENERIC_CORECore cells
Core Cell (1.0V)FSD0K_A_GENERIC_CORECore cells
I/O (2.5V)FSD0K_A_T25_GENERIC_IOTrue 2.5V programmable I/O
I/O (3.3V)FSD0K_A_T33_GENERIC_IOTrue 3.3V programmable I/O
1P SRAMFSD0K_A_SHSynchronous, high density single port SRAM
Dual Port SRAMFSD0K_A_SJSynchronous, dual port RAM
1P RFFSD0K_A_SYSynchronous, single port register file
2P RFFSD0K_A_SZSynchronous, dual port register file
VIA ROMFSD0K_A_SPSynchronous, via1 programmable ROM
PLL IPFXPLL110HD0K (not available yet)Phase locked loop
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