IP & Libraries > Standard cell libraries > faraday

Standard cell libraries -- Faraday

IMEC has signed an agreement with Faraday to distribute Faraday's UMC sponsored libraries (no GDS) under following conditions:

*Universities and research institutes can get access free of charge to Faraday libraries for UMC technologies for non-commercial design activities

*Companies can get access to Faraday libraries for UMC technologies for commercial design activities provided a tape-out fee is paid to IMEC (when companies have a direct license from Faraday, this tape-out fee is waived)

 


Process
IP
IP Name
Description
From Faraday

L250 GII

 Core Cell FS90A_C_GENERIC_CORE Core cells
I/O FS90A_C_T33_GENERIC_IO
FS90A_C_50VT_GENERIC_IO
FS90A_C_T33_ANALOGESD
FS90A_C_T25_OSC_HIGH_IO

True 3.3V I/O
3.3V I/O with 5V tolerance
3.3V analog ESD protection
3.3V 1M~66M crystal oscillator IO
1P SRAM FS90A_C_SU Synchronous, high speed single port RAM
1P RF FS90A_C_SY Synchronous, single port register file
2P RF FS90A_C_SZ Synchronous, two port register file
VIA ROM FS90A_C_SP Synchronous, via1 programmable ROM
PLL IP PLL9019 Phase locked loop




Process
IP
IP Name
Description
From Faraday

L180 GII

 Core Cell FSA0A_C_GENERIC_CORE Core cells
I/O FSA0A_C_T33_GENERIC_IO FSA0A_C_50VT_GENERIC_IO
FSA0A_C_T33_ANALOGESD_IO
FSA0A_C_TMVH33L25_SSTL2C2WLVTTL_IO		 True 3.3V I/O
3.3V I/O with 5V tolerance
3.3V analog ESD protection
3.3V SSTL-2 CLASSII LVTTL COMBO I/O
1P SRAM FSA0A_C_SU Synchronous, high speed single port RAM
Dual Port SRAM FSA0A_C_SJ Synchronous, dual port RAM
1P RF FSA0A_C_SY Synchronous, single port register file
2P RF FSA0A_C_SZ Synchronous, two port register file
VIA ROM FSA0A_C_SP Synchronous, via1 programmable ROM
FXDLL311HA0A_DP
FXLVRX020HA0A_DP
FZOTG110HA0A_DP		 Delay-Locked LOOP
Low Voltage Differential Signal Receiver
USB ON-THE-GO Transceiver
PLL IP FXPLL031HA0A_BPGD Phase locked loop




Process
IP
IP Name
Description
From Faraday

L180 LL

 Core Cell FSA0L_A_GENERIC_CORE Core cells
I/O FSA0L_A_T33_GENERIC_IO
FSA0L_A_50VT_GENERIC_IO
FSA0L_A_T33_ANALOGESD_IO
FSA0L_A_T33_OSC_HIGH_IO		 True 3.3V I/O
3.3V I/O with 5V tolerance
3.3V analog ESD protection
3.3V 1M~66M crystal oscillator IO 
1P SRAM FSA0L_A_SH Synchronous, high density single port RAM
Dual Port SRAM FSA0L_A_SJ (not available) Wait for UMC 8T bit cell to start design
1P RF FSA0L_A_SY Synchronous, single port register file
2P RF FSA0L_A_SZ (not available) Wait for UMC 8T bit cell to start design
VIA ROM FSA0L_A_SP Synchronous, via1 programmable ROM


Process
IP
IP Name
Description
From Faraday

L180 MMRF

 Core Cells FSA0M_A_GENERIC_CORE CORE cells
I/O FSA0M_A_T33_GENREIC_IO True 3.3V I/O
I/O FSA0M_A_50VT_GENERIC_IO 3.3V I/O with 5V tolerance
1P SRAM FSA0M_A_SU Synchronous, high density single port RAM
Dual Port SRAM FSA0M_A_SJL Wait for UMC 8T bit cell to start design




Process
IP
IP Name
 Description
From Faraday

L180 CIS

 Core Cells FSA0I_R_GENERIC_CORE CORE cells
I/O FSA0I_R33_T33_GENREIC_IO True 3.3V standard I/O cell library
I/O FSA0I_A33_T33_GENERIC_IO True 3.3V I/O
I/O FSA0I_A33_50VT_GENERIC_IO 3.3V I/O with 5V tolerance
1P SRAM FSA0I_A_SL Synchronous, high density single port RAM




Process
IP
IP Name
Description
From Faraday

L130 HS/FSG

 Core Cell FSC0H_D_GENERIC_CORE Core cells
I/O FSC0H_A33_T33_GENERIC_IO
FSC0H_A33_50VT_GENERIC_IO
FOC0H_A33_T33_ANALOGESD_IO
FOC0H_A33_T33_OSC_HIGH_IO
FOC0H_O33_50VT_GENERIC_IO
FOC0H_O33_T33_ANALOGESD_IO		 True 3.3V I/O
3.3V I/O with 5V tolerance
3.3V analog ESD protection
3.3V 1M~66M crystal oscillator IO
3.3V I/O with 5V tolerance (BOAC)
3.3V analog ESD protection (BOAC)
1P SRAM FSC0H_D_SH Synchronous, low leakage single port SRAM
Dual Port SRAM FSC0H_D_SJ Synchronous, low leakage dual port SRAM
1P RF FSC0H_D_SY Synchronous, low leakage single port register file
2P RF FSC0H_D_SZ Synchronous, low leakage dual port register file
VIA ROM FSC0H_D_SP Synchronous, via1 programmable ROM
PLL IP FXPLL010HC0L_APGD Phase locked loop




Process
IP
IP Name
Description
From Faraday

L130 LL/FSG

 Core Cell FSC0L_D_GENERIC_CORE Core cells
I/O FSC0L_D_T33_GENERIC_IO
FSC0L_D_50VT_GENERIC_IO
FOC0L_A33_T33_ANALOGESD_IO
FOC0L_A33_T33_OSC_HIGH_IO
FOC0L_A33_T33_OSC_LOW_IO		 True 3.3V I/O
3.3V I/O with 5V tolerance
3.3V analog ESD protection
3.3V 1M~66M crystal oscillator IO
3.3V 32K~1M crystal oscillator IO
1P SRAM FSC0L_D_SH Synchronous, low leakage single port SRAM
Dual Port SRAM FSC0L_D_SJ Synchronous, low leakage dual port SRAM
1P RF FSC0L_D_SY Synchronous, low leakage single port register file
2P RF FSC0L_D_SZ Synchronous, low leakage dual port register file
VIA ROM FSC0H_D_SP Synchronous, via1 programmable ROM
PLL IP FXPLL010HC0L_APGD Phase locked loop




Process
IP
IP Name
Description
From Faraday

L130E SP/FSG

 Core Cell FSC0G_D_GENERIC_CORE Core cells
I/O FSC0G_D_T33_GENERIC_IO
FSC0G_D_50VT_GENERIC_IO
FOC0G_A33_T33_ANALOGESD_IO
FOC0G_A33_T33_OSC_HIGH_IO		 True 3.3V I/O
3.3V I/O with 5V tolerance
3.3Vanalog ESD protection
3.3V 1M~66M crystal oscillator IO
1P SRAM FSC0G_D_SH Synchronous, standard performance single port SRAM
Dual Port SRAM FSC0G_D_SJ Synchronous, standard performance dual port SRAM
1P RF FSC0G_D_SY Synchronous, standard performance single port register file
2P RF FSC0G_D_SZ Synchronous, standard performance dual port register file
VIA ROM FSC0H_D_SP Synchronous, via1 programmable ROM
PLL IP FXPLL010HC0G_APGD Phase locked loop




Process
IP
IP Name
Description
From Faraday

L130E Fusion

 1P SRAM FSC0U_D_SH Synchronous, fusion single port SRAM
Dual Port SRAM FSC0U_D_SJ Synchronous, fusion dual port SRAM
1P RF FSC0U_D_SY Synchronous, fusion single port register file
2P RF FSC0U_D_SZ Synchronous, fusion dual port register file
VIA ROM FSC0H_D_SP Synchronous, via1 programmable ROM
PLL IP FXPLL010HC0U_APGD Phase locked loop




Process
IP
IP Name
Description
From Faraday

L130 HGMM

 I/O FOC0M_A33_50VT_GENERIC_IO
FOC0M_A33_T33_GENERIC_IO		 3.3V I/O with 5V tolerance
True 3.3V I/O




Process
IP
IP Name
Description
From Faraday

L90 SP Low-K (RVT)

 Core Cell FSD0A_B_GENERIC_CORE
FSD0A_B_GENERIC_CORE		 Core cells 1.0V
Core cells 1.2V
I/O FOD0A_B25_T25_GENERIC_IO True 2.5V Generic IO Library
I/O FOD0A_B33_T33_GENERIC_IO True 1.0/3.3V standard I/O cell Library (3.3V Generic IO)
I/O FOD0A_B25_T33_GENERIC_IO
FOD0A_B25_33VT_GENERIC_IO
FOD0A_B33_T33_ANALOGESD_IO
FOD0A_B25_T25_OSC_HIGH_IO
 2.5V OD 3.3V IO true 3.3V standard IO cell Library using 3.3V GOX52 IO
2.5V with 3.3V tolerant generic IO cells
True 1.0/3.3V standard IO cell library (3.3V analog IO)
2.5V 1MHz ~ 66MHz programmable Crystal Oscillator I/O cells
1P SRAM FSD0A_B_SH Synchronous, single port SRAM
Dual Port SRAM FSD0A_B_SJ Synchronous, dual port RAM
1P RF FSD0A_B_SY Synchronous, single port register file
2P RF FSD0A_B_SZ Synchronous, dual port register file
VIA ROM FSD0A_B_SP Synchronous, via1 programmable ROM
PLL IP FXPLL110HD0A Phase locked loop
L90 SP Low-K (HVT) Core Cell FSD0C_A_GENERIC_CORE Corel cells 1.0V
Core Cell FSD0C_A_GENERIC_CORE Core cells 1.2V
L90 SP Low-K (LVT) Core Cell FSD0T_A_GENERIC_CORE_1D0V Core cells 1.0V




Process
IP
IP Name
Description
From Faraday

L90 LL Low-K (RVT)

 Core Cell FSD0K_A_GENERIC_CORE Core cells
Core Cell (1.0V) FSD0K_A_GENERIC_CORE Core cells
I/O

FSD0K_B25_T25_GENERIC_IO
FSD0K_B33_T33_GENERIC_IO
FSD0K_B25_33VT_GENERIC_IO

 True 2.5V programmable I/O
True 1.0/3.3V standard IO cell library (3.3V Generic IO
2.5V with 3.3.V tolerant generic I/O cells
I/O FSD0K_B33_T33_ANALOGESD_IO
FSD0K_B25_T25_OSC_HIGH_IO
FSD0K_B25_T25_OSC_LOW_IO		 True 1.0/3.3V standard IO cell Library (3.3V analog IO)
2,5V 1MHz ~ 66MHz Programmable Crystal Oscillator I/O Cells
2,5V 1MHz ~ 66MHz Programmable Crystal Oscillator I/O Cells
1P SRAM FSD0K_A_SH Synchronous, high density single port SRAM
Dual Port SRAM FSD0K_A_SJ Synchronous, dual port RAM
1P RF FSD0K_A_SY Synchronous, single port register file
2P RF FSD0K_A_SZ Synchronous, dual port register file
VIA ROM FSD0K_A_SP Synchronous, via1 programmable ROM
PLL IP FXPLL110HD0K Phase locked loop
L90 LL Low-K (HVT) Core Cell FSD0J_A_GENERIC_CORE Corel cells 1.0V
Core Cell FSD0J_A_GENERIC_CORE Core cells 1.2V
L90 LL Low-K (LVT) Core Cell FSD0W_A_GENERIC_CORE Core cells 1.0V




Process
IP
IP Name
Description
From UMC

Full layout upon approval

L65 Low Leakage

 Core Cell UMK65LSCLLMVBBH - LL - HVT
UMK65LSCLLMVBBL - LL - LVT
UMK65LSCLLMVBBR - LL - RVT

UMC 65nm Low-K 1.2V/1.0V
Tapless Standard Cell Library

I/O UM065GIOLL25MVIR - LL - RVT
UM065GIOLL33GPIR - LL - RVT
UM065GIOLL18GPIR - LL - RVT
UM065GIOLL25MVSR - LL - RVT
UM065GIOLL33GPIH - LL - HVT

UMC 65nm Low-K 3.3V / BOAC In-line IO Library (Digital+ Analog ESD)
UMC 65nm Low-K 3.3V / BOAC In-line IO Library
UMC 65nm Low-K 1.8V / BOAC In-line IO Library
UMC 65nm Low-K 1.8V-2.5V-3.3V / BOAC Stagger IO Library
UMC 65nm Low-K 3.3V / BOAC In-line IO Library




Process
IP
IP Name
Description
From Faraday

L65 Low Leakage RVT

 1P SRAM FSE0K_A_SH Synchronous, high density single port RAM
Dual Port SRAM FSE0KA_A_SJ Synchronous, dual port RAM
1P RF FSE0K_A_SY Synchronous, single port register file
2P RF FSE0K_A_SZ Synchronous, dual port register file
VIA ROM FSE0K_A_SP Synchronous, via1 programmable ROM
1P SRAM (RED) FSE0K_A_SHRED Synchronous, high density single port SRAM with row redundancy
Dual Port SRAM (RED) FSE0K_A_SJRED Synchronous, dual port RAM with redundancy features




Process
IP
IP Name
Description
From UMC

Full layout upon aprroval

L65 SP

 Core Cell UMK65LSCSPMVL9B - SP - logic mixed mode
UMK65LSCSP08BBRCCS - SP - RVT
UMK65LSCSP10BBRCCS - SP - RVT
UMK65LSCSPMVBBH - SP - HVT
UMK65LSCSPMVBBR - SP - HVT
UMK65LSCSP10BBHCCS - SP - HVT
UMK65LSCSP10BSHCCS - SP - SHVT
 Standard Cells Multi Voltage
Standard Cells 0.8V
Standard Cells 1.0V
Standard Cells Multi Voltage
Standard Cells Multi Voltage
Standard Cells 1.0V
Standard Cells 1.0V
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