Technologies

EUROPRACTICE has signed agreements with several leading foundries and library vendors to offer low cost ASIC prototyping (MPW) and small-medium volume production.

The offering includes IC technologies from the following foundries

	ON Semi (formerly AMIS) The technologies offered include basic 0.7µ, 0.5µ and 0.35µ CMOS logic and mixed and high-voltage 0.7µ, 0.5µ and 0.35µ CMOS. The ON Semi design rules, spice parameters, design manuals and standard cell libraries and design kits are available through EUROPRACTICE after signing the DKLA. For reduced-cost single project engineering runs, MLM (Multi Level Mask) mask set is possible. ON Semi offers for all their technologies the possibility of stitching, allowing to fabricate large image sensor chips (larger than reticle field).
	austriamicrosystems The technologies offered include basic 0.8µ - 0.18µ CMOS logic, mixed and high-voltage 0.8µ and 0.18µ CMOS, high-speed 0.35µ SiGe BiCMOS and 0.35µ CMOS OPTO for image sensors. The austriamicrosystems design rules, spice parameters and design manuals are available through EUROPRACTICE after signing the CA and NDA.
	IHP The technologies offered include high-speed 0.25µ - 0.18µ SiGe:C BiCMOS. The IHP design rules, spice parameters and design manuals are available through EUROPRACTICE after signing the NDA.
	LFoundry LFoundry's initial offering will be the LF150 modular 0.15µm Low Power and RF CMOS process, providing up to six levels of Aluminum interconnects, MIM capacitor, polymide passivation and I/O voltages of 1.8V, 3.3V and 5.0V. All silicon is produced at LFoundry's state-of-the-art 200mm wafer fab in Landshut, Germany. A large portfolio of process-proven libraries, IP, design tools and reference flows is supported. Low volume manufacturing with a flexible approach of the customer requirements is also offered at low cost.
	TSMC TSMC is offering a wide range of technologies. Universities and research institute Universities and research institutes can only access 0.25u, 0.18u, 0.13u, 90nm and 65nm CMOS based logic and mixed-signal/RF technologies (see procedures under Foundry Access). The TSMC design rules, spice parameters and design kits are available through EUROPRACTICE after signing the NDA. Standard cell libraries and design kits for the TSMC technologies are available from companies like ARM (artisan). Companies Companies can access a wide range of TSMC technologies ranging from 0.5u down to 40nm, including all flavors available such as logic, mixed-signal/RF, e-flash, SiGe, CIS (CMOS Imaging Sensor),... Companies can get access to these technologies as well as for prototyping as for volume production
	UMC The technologies offered include 0.25µ, 0.18µ, 0.13µ and 90nm CMOS logic and mixed. In addition also the 0.35µ, 0.25µ and 0.18µ CIS (CMOS Imaging Sensor) technologies are offered for image sensors. The UMC design rules, spice parameters and design kits are available through EUROPRACTICE after signing the NDA. Standard cell libraries and design kits for the UMC technologies are available from Faraday.
Microsystems & MEMS Technologies :
	TRONICS The MEMSOI MPW service provides access to Tronics 60µm thick SOI High Aspect Ratio Micromachining (SOI-H.A.R.M.). The technology is developed to manufacture high performance custom inertial sensors, using capacitive comb drive structures for sensing and actuation and can be used for a variety of devices like accelerometers and gyros, resonators, grippers, mechanical switches and microfluidics structures.
	MEMSCAP The Multi-User MEMS Processes, or MUMPs®, is a well-established program that has run consistently since 1992. Over 80 full process runs have been completed and shipped over that time to hundreds of organizations. MEMSCAP offers three unique stand-alone, multi-mask MEMS processes in MUMPs® : PolyMUMPs, SOIMUMPs, and MetalMUMPs.
	imec SiGeMEMS Imec’s CMORE Silicon Germanium MEMS platform technology, referred to as SiGeMEMS, is designed as a monolithic integration of CMOS and MEMS. Systems integrating MEMS devices with the driving and readout electronics on the substrate lead to better performances in terms of signal to noise ratio through reduced interconnect parasitic resistance and capacitance, allow for smaller die size and package, and also for lower power consumption. SiGeMEMS is built based on a CMOS-first route which allows state-of-the-art CMOS foundries to be employed. EUROPRACTICE offers a fixed baseline process of SiGeMEMS in a Multi-Project Wafer Service. This unique baseline process consists of MEMS structures defined by an electrode layer and a 4μm-thick SiGe-mechanical layer on top of a TSMC 0.18um CMOS wafer. Nanogaps of 500nm will allow fabrication of extremely small features. A standalone MEMS version, identical but processed on a wafer with a single metal layer, is available for initial prototyping.