| Process Name | C07M |
| Route | C07-D | C07-A | I2T30 | I2T30E | I2T100 |
| Geometry | 0.7um | 0.7um | 0.7um | 0.7um | 0.7um |
| PROCESS FEATURE |
|
|
|
| Wafersize (inch) | 6 |
| Substrate Type | Pepi on P |
| Isolation | LOCOS |
| Poly Layers | 1 | 1 | 1 | 1 | 2 |
| Poly Pitch (um) | 1.5 |
| Metal Layers (Min) | 2 |
| Metal Layers (Max) | 3 |
| Metal 1/2/3/4/5 Pitch (um) | 1.8 / 2.2 / 3 |
| Gate Oxide Thickness (nm) | 17 | 17 | 17 | 17 | 17 / 42 |
| Operating Voltage (V) | 3.3 / 5 | 3.3 / 5 | 30 | 30 | 100 |
| Number of Masks (metal option) | 11 / 13 | 14 / 16 | 14 / 16 | 15 / 17 | 22 / 24 |
| DEVICE CHART |
|
|
|
| N/PMOS Saturation Current (uA/um) | 358 / 176 |
| Poly resistors (kΩ/sq) | N/A | 2 | 2 | 2 | 2 |
| Precision Capacitor Poly/Poly (fF/um2) | N/A | N/A | N/A | N/A | 0.36 |
| Precision Capacitor Poly/Diffusion (fF/um2) | N/A | 0.75 | 0.75 | 0.75 | 0.75 |
| Precision Capacitor MIMC (fF/um2) | N/A |
| Number of Core cells | 126 |
| Gate density (NAND2 equiv.) (kgates/mm2) | 1.25 |
| Logic Delay of NAND2 (ps) | 200 |
| NAND2 Area (um2) | 465 |
| Average Powerdissipation (NAND2) (uW/MHz) | 3.2 |
| I/O cells | 108 |
| Special I/O cells | N/A |
| RAM (Single Port) (kbits/mm2) | Y |
| RAM (Dual Port) (kbits/mm2) | Y |
| ROM (kbits/mm2) | Y |
| Analog library | N/A | Y | Y | Y | Y |
| HV transistors (V) | 40 | 40 | 40 | 40 | 100 |
| ADC | N/A | 8 bit | 8 bit | 8 bit | 8 bit |
| DAC | N/A | 8 bit | 8 bit | 8 bit | 8 bit |
| OPAMPS | N/A | Y | Y | Y | Y |
| OTP | N/A | N/A | N/A | N/A | Y |
| EEPROM | N/A |
| N channel DMOS | N/A | Y | Y | Y | Y |
| P channel DMOS | N/A | N/A | N/A | N/A | Y |
| Floating NMOS | N/A | N/A | N/A | N/A | Y |
| Floating PMOS | N/A | N/A | N/A | N/A | Y |
| Floating NDMOS | N/A | N/A | N/A | Y | Y |
| Floating PDMOS | N/A | N/A | Y | Y | Y |
| Bipolars (vertical) | Y |