| TSMC 0.25 um technology overview (MPW): |
| Technology | Logic | Logic | MS/RF | MS/RF |
| Geometry | 0.25um | 0.25um | 0.25um | 0.25um |
| Device Application | General Purpose | General Purpose | MS CMOS (1P5M) * | MS CMOS (1P5M) * |
| Core Voltage (V) | 2.5 | 2.5 | 2.5 | 2.5 |
| I/O Voltage (V) | 3.3 | 5 | 3.3 | 5 |
| Poly Layers | 1 | 1 | 1 | 1 |
| Metal Layers (Min) | 3 | 3 | 3 | 3 |
| Metal Layers (Max) | 5 | 5 | 5 | 5 |
| RO Speed (ps/gate) | 41 | 41 | 41 | 41 |
| BEOL Dielectric | Oxide IMD | Oxide IMD | Oxide IMD | Oxide IMD |
| BEOL Metal | Al | Al | Al | Al |
| PROCESS FEATURE | | | | |
| Well Formation | Retrograde well | Retrograde well | Retrograde well | Retrograde well |
| Isolation | STI | STI | STI | STI |
| Gate Materials | Silicide | Silicide | Silicide | Silicide |
| Silicide Material | Ti-salicide | Ti-salicide | Ti-salicide | Ti-salicide |
| Gate Dielectric tox(core) | 50A | 50A | 50A | 50A |
| Gate Dielectric tox(I/O) | 70A | 120A | 70A | 120A |
| Emb-6T SRAM cell (um2) | 10.95/7.56 | 10.95/7.56 | 10.95/7.56 | 10.95/7.56 |
| DEVICE CHART (CORE) | | | | |
| nMOS--Isat (uA/um) | 600 | 600 | 600 | 600 |
| nMOS--Vt(V) | 0.53 | 0.53 | 0.53 | 0.53 |
| nMOS--Ioff_max (nA/um) | 0.1 | 0.1 | 0.1 | 0.1 |
| pMOS--Idsat (uA/um) | 270 | 270 | 270 | 270 |
| pMOS--Vt(V) | -0.53 | -0.53 | -0.53 | -0.53 |
| pMOS--Ioff_max (nA/um) | 0.1 | 0.1 | 0.1 | 0.1 |
| DEVICE CHART (I/O) | | | | |
| Vdd(V) | 3.3 | 5 | 3.3 | 5 |
| nMOS--Isat (uA/um) | 560 | 530 | 560 | 560 |
| nMOS--Vt(V) | 0.5 | 0.83 | 0.5 | 0.8 |
| nMOS--Ioff_max (nA/um) | 0.1 | 0.1 | 0.1 | 0.1 |
| pMOS--Idsat (uA/um) | 240 | 240 | 240 | 240 |
| pMOS--Vt(V) | -0.82 | -0.82 | -0.82 | -0.82 |
| pMOS--Ioff_max (nA/um) | 0.1 | 0.1 | 0.1 | 0.1 |
| MS/RF PROCESS MODULE | | | | |
| Core transistor Vt | N/A | N/A | Nominal, Medium, Native, Zero | Nominal, Medium, Native, Zero |
| PiP | N/A | N/A | Available C = 1.0fF/um^2 (*) | Available C = 1.0fF/um^2 (*) |
| MiM | N/A | N/A | Available C = 1.0fF/um^2; Q >50 for C=0.9fF @2.4GHz | Available C = 1.0fF/um^2; Q >50 for C=0.9fF @2.4GHz |
| Inductor | N/A | N/A | Available 1.5um(Al); Q >6 for L=4nH @2.4GHz | Available 1.5um(Al); Q >6 for L=4nH @2.4GHz |
| Hi Resistors | N/A | N/A | 400 Ohm/Sq | 400 Ohm/Sq |
| Varactor | N/A | N/A | MOS and Junction Varactors available | MOS and Junction Varactors available |
| Triple well | N/A | N/A | DNW Optional | DNW Optional |
| BJT DEVICE | | | | |
| Hfe | N/A | N/A | N/A | N/A |
| VA(V) | N/A | N/A | N/A | N/A |
| BV ceo(V) | N/A | N/A | N/A | N/A |
| Ft(GHz) | N/A | N/A | N/A | N/A |
| Fmax(GHz) | N/A | N/A | N/A | N/A |
| Ipeak(mA) | N/A | N/A | N/A | N/A |
| MORE FEATURES | | | | |
| Default # of masks (exclusive opt. masks) | 25 | 26 (extra 2.5V VTP mask)** | 25 | 26 (extra 2.5V VTP mask)** |
| # optional masks | 2 | 2 | 11 | 7 |
| All Optional masks | ESD,PM | ESD,PM, | ESD,DNW,VTM_N,VTM_P, (BPI,CTP)*, LPP,VTD_N, VTD_P,CTM,PM | ESD,DNW,(BPI,CTP)*, LPP,CTM,PM |
| EP MPW optional masks | ESD,PM | ESD,PM | ESD,DNW,(BPI,CTP)*, CTM,PM | ESD,DNW,(BPI,CTP)*, CTM,PM |
| Made in Fab | Fab3,Fab8, Fab10 (all 8-inch) | Fab3,Fab8, Fab10 (all 8-inch) | Fab3,Fab8, Fab10 (all 8-inch) | Fab3,Fab8, Fab10 (all 8-inch) |
| Available PDK for Cadence | 1 PDK for Logic and MS/RF (CR025G) | |||
| Available PDK for Mentor | N/A | |||
| * Only 1P5M supported by EUROPRACTICE, 2P5M not supported. Extra optional mask BPI and CTP for PiP capacitor not possible for 1P5M process, only for 2P5M. | ||||
| ** For 2.5V/5V process, VTP (117) extra mask is needed to block the 5.0V PMOS | ||||