| Process Name |
| L250 |
| MixedMode/RF |
| Process technology specifications | units |
|
| Substrate Type |
| P-substrate |
| Nwell - Sal ( Poly[n][p] / Active[n][p] ) Unsalicided ( Poly[n][p] / Active[n][p] ) | Ohm/sq | 400 - ( [2.5] [2.5] / [2.5] [2.5] ) ( [133] [309] / [79] [79] ) |
| Wafer size (6) / available die thicknesses |
| 8 Inch / 29 Mils - 11 Mils |
| High Ohmic Resistor (HR) | Ohm/sq | 948 |
| Metal Metal Cap (MiM cap) | fF/µm² | 1 |
| Low Vt / Zero VT implant |
| Y/Y |
| Twin well / Triple well / Thick gate for 3.3V |
| Y / Y / Y |
| Number of Poly/Metal Layers | # | 1P 5M |
| Metal1/2/3/4/5 /6 /7/8 Pitch | µm | 0.96/0.8/0.8/0.8/0.64 |
| Min drawn MOS Length (regular/3.3V) | µm | 0.24 / 0.34 |
| Min diffusion width for MOS | µm | 0.3 |
| Operating Voltage | V | 2.5 / 3.3 |
| Vton(N / P) | V | 0.54 / -0.58 |
| Ioff(N / P) core transistor (VD = VDD, Vg = 0V) | pA/µm | 3 / -2 |
| Number of Masks (all options included) | # | 35 |
| Ring Oscillator stage delay ( 2 conditions) | pSec/stage | 40 (@2.5V) 55 (@3.3V) |
| RF Top Level Metal Pitch | µm | 2.2 |
| RF Top Level Thickness | kA | 20 |
| Ft | GHz | 32GHz @ 140µA/um Vg/Vd=1.5V/2.5V |
| Fmax | GHz | 30GHz @138µA/um Vg/Vd=1.5V/2.5V |
| Cadence Design Kit |
| MixedMode + RF |
|
|
|
|
|
|
|
|
|
|
|