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UMC 0.18 um technology overview (MPW):


Process Name
L180
Process technology specifications units Logic GII - MMC Logic - Low Leakage MixedMode/RF EFLASH/EEPROM
Substrate Type
P-substrate P-substrate P-substrate P-substrate
Nwell - Sal ( Poly[n][p] / Active[n][p] ) Unsalicided ( Poly[n][p] / Active[n][p] ) Ohm/sq 415 - ( [8] [8] / [8] [8] ) ( [80] [158] / [126] [360] ) 415 - ( [8] [8] / [8] [8] ) ( [80] [158] / [126] [360] ) 415 - ( [8] [8] / [8] / [8] ) ( [80] [158] / [113] [352] ) 415 - ( [8] [8] / [8] / [8] ) ( [80] [158] / [113] [352] )
Wafer size (6) / available die thicknesses
8 Inch / 29 Mils - 11 Mils 8 Inch / 29 Mils - 11 Mils 8 Inch / 29 Mils - 11 Mils 8 Inch / 29 Mils - 11 Mils
High Ohmic Resistor (HR) Ohm/sq - - 1039 1039
Metal Metal Cap (MiM cap) fF/µm² 1 - 1 1
Low Vt / Zero VT implant
- - Y / Y Y
Twin well / Triple well / Thick gate for 3.3V
Y / - /Y Y / - /Y Y / Y /Y Y / N /Y
Number of Poly/Metal Layers # 1P 6M 1P 6M 1P 6M 2P 6M
Metal1/2/3/4/5 /6 /7/8 Pitch µm 0.48/0.56/0.56/0.56/0.56/0.88 0.48/0.56/0.56/0.56/0.56/0.88 0.48/0.56/0.56/0.56/0.56/0.88 0.48/0.56/0.56/0.56/0.56/0.88
Min drawn MOS Length (regular/3.3V) µm 0.18 / 0.34 0.18 / 0.34 0.18 / 0.34 0.18 / 0.34
Min diffusion width for MOS µm 0.24 0.24 0.24 0.24
Operating Voltage V 1.8 / 3.3 1.8 / 3.3 1.8 / 3.3 1.8 / 3.3 / 6.5 / 14
Vton(N / P) V 0.5 / -0.5 0.61 / -0.6 0.51 / -0.5 0.51 / -0.5
Ioff(N / P) core transistor (VD = VDD, Vg = 0V) pA/µm 15 / -10 2 / -2 7.6 / -8 7.6 / -8
Number of Masks (all options included) # 27 28 35 35 + EFLASH
Ring Oscillator stage delay ( 2 conditions) pSec/stage 27 (@1.8V) 55 (@3.3V) 36 (@1.8V) 55 (@3.3V) 27 (@1.8V) 55 (@3.3V) 27 (@1.8V) 55 (@3.3V)
RF Top Level Metal Pitch µm - - 2.2 2.2
RF Top Level Thickness kA - - 20 20
Ft GHz - - 49GHz @ 300µA/um Vg/Vd=1.2V/1.8V -
Fmax GHz - - 34GHz @ 300µA/um Vg/Vd=1.2V/1.8 -
DESIGNKITS
Cadence Design Kit
Logic GII + MMC Logic - Low Leakage MixedMode + RF EFLASH/EEPROM
Synopsys Design Kit
N/A








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