Austriamicrosystems design kits

HIT-Kit

The High Performance Interface Tool Kit (HIT-Kit) is a unique utility kit consisting of software programs and libraries which contain full frontend (symbol, schematic, simulation model) and backend (placement outlines, full layout) information for the development of digital, analog and mixed signal circuits in a Cadence Design Systems, Mentor Graphics or Synopsys CAE design environment.

To cover a wide range of hardware platforms, the HIT-Kit is available to the growing number of users in the mixed signal domain for PC, Sun and HP workstations.

Depending on the customer's design environment, needs and experience, several versions of the HIT-Kit are available.

HIT-Kit Versions

*HIT-Kit Cadence

• Framework
  Design FrameworkII (analogArtist)
  
• Schematic Design Creation
  Composer Circuit Design Entry
  
• Register Transfer Level Creation
  HDL Designer [Mentor]
  
• Behavioral Modelling
  S VHDL * Verilog * Verilog A * SpectreHDL * Verilog AMS * VHDL AMS
  
• Logic Synthesis & Optimization
  Design Compiler [Synopsys] * BuildGates /PKS [Cadence]
  
• ATPG
  Tetramax [Synopsys] * Fastscan/Flextest [Mentor]
  
• Simulation
  
  • Behavioral
    Verilog-XL * NCSim * Spectre HDL * ModelSim [Mentor]
    
  • Digital
    Verilog-XL * NCSim * ModelSim [Mentor]
    
  • Analog
    Spectre * UltraSim * HSIM [Synopsys] * Eldo [Mentor] * hspice [Synopsys]
    
  • RF
    Spectre RF * ADS [Agilent]
    
  • Mixed Signal
    SpectreVerilog * AMS Designer
    
• Place & Route
  First Encounter * Silicon Ensemble * IC-Craftsman
  
• Layout
  Virtuoso Layout Editor * ROD Pcells (available in Mixed-Signal HIT-Kit only)
  
• Verification
  Assura * Calibre [Mentor] * Diva
  

* HIT-Kit - Mentor

• Framework
  Falcon Framework
  
• Schematic Design Creation
  Design Architect IC
  
• Register Transfer Level Creation
  HDL Designer
  
• Behavioral Modelling
  VHDL * HDL-A * Verilog * VHDL-AMS * Verilog-AMS
  
• Logic Synthesis & Optimization
  Design Compiler [Synopsys] * BuildGates/PKS [Cadence]
  
• ATPG
  Tetramax [Synopsys] * Fastscan/Flextest
  
• Simulation
  
  • Behavioral
    ModelSim (VHDL/Verilog) * Eldo HDL-A * NCSim [Cadence]
    
  • Digital
    ModelSim (VHDL/Verilog) * NCSim [Cadence]
    
  • Analog
    Eldo/Eldo RF
    
  • Mixed Signal
    AdvancedMS (available in Mixed-Signal HIT-Kit only)
    
• Place & Route
  AutoCells * Silicon Ensemble [Cadence]
  
• Layout
  IC Station * Device Generators (available in Mixed-Signal HIT-Kit only)
  
• Verification
  Calibre/Calibre xRC * ICverify
  

Europractice distributes 2 versions of the austriamicrosystems HIT-Kits free of charge,

*Digital HIT-Kit;

• The Digital HIT-Kit without Pcell library (device generator) is distributed to all industrial Europractice members
• The Digital HIT-Kit + Pcell library(device generator) is distributed to all Academical Europractice members

*Mixed Signal HIT-Kit(subject to license fee);
the Mixed Signal HIT-Kit for creating custom Analog and Mixed-Signal designs. It is an extension to the Digital HIT-Kit and includes custom device generator (PCells), Package models, 3-Bus libraries, RF Pads, and a complete set of LV analog cells for mixed-mode designs and is therefore subject to license fee(10.9KEURO).

More information on the HIT-Kit can be found on the austriamicrosystem TECHNOLOGICAL website:

http://asic.austriamicrosystems.com